Non-volatile semiconductor memory device in which selection gate transistors and memory cells have different structures
US6835987B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2002 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Jan 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetrical to the shape of the drain diffusion layer region thereof below the selection gate transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.