Semiconductor memory device capable of realizing a chip with high operation reliability and high yield
US6836444B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2003 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Jun 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array comprising memory cell units arranged in an array form, first blocks including first memory cell units each having at least one memory cell and at least one selection gate transistor, and second blocks including second memory cell units each having at least one memory cell and at least one selection gate transistor, wherein the first blocks are arranged on both end portions of the memory cell array, the second blocks are arranged in another portion, and a structure of the first memory cell units on the end portions of the memory cell array is different from a structure of the second memory cell units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.