Pipelined hardware implementation of a neural network circuit
US6836767B2 · kind B2 · utility
27Cited by
10References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 3, 2001 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Jul 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a first aspect, a pipelined hardware implementation of a neural network circuit includes an input stage, two or more processing stages and an output stage. Each processing stage includes one or more processing units. Each processing unit includes storage for weighted values, a plurality of multipliers for multiplying input values by weighted values, an adder for adding products outputted from product multipliers, a function circuit for applying a non-linear function to the sum outputted by the adder, and a register for storing the output of the function circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.