Chad B. McBride
52Patents
6h-index
30Co-inventors
72Inventor score
Filing activity: May 1, 1998 → Feb 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6836767B2 | Pipelined hardware implementation of a neural network circuit | Physics | 27 | Expired |
| US6453366B1 | Method and apparatus for direct memory access (DMA) with dataflow blocking for users | Physics | 10 | Expired |
| US7458174B1 | Needle punch stretch hoop | Textiles; Paper | 8 | Active |
| US6289430A | Method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags | Physics | 7 | Expired |
| US5977837A | Phase selector for external frequency divider and phase locked loop | Emerging Cross-Sectional Technologies | 7 | Expired |
| US6601122B1 | Exceptions and interrupts with dynamic priority and vector routing | Physics | 6 | Expired |
| US10628345B2 | Enhancing processing performance of a DNN module by bandwidth control of fabric interface | Emerging Cross-Sectional Technologies | 5 | Active |
| US7543204B2 | Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree | Physics | 4 | Active |
| US6011412A | Frequency shift detection circuit with selectable granularity | Electricity | 3 | Expired |
| US8327075B2 | Methods and apparatus for handling a cache miss | Physics | 3 | Active |
| US11100390B2 | Power-efficient deep neural network module configured for layer and operation fencing and dependency management | Emerging Cross-Sectional Technologies | 3 | Active |
| US7509611B2 | Heuristic clustering of circuit elements in a circuit design | Physics | 3 | Active |
| US9146835B2 | Methods and systems with delayed execution of multiple processors | Physics | 3 | Active |
| US7634591B2 | Method and apparatus for tracking command order dependencies | Physics | 3 | Active |
| US10795836B2 | Data processing performance enhancement for neural networks using a virtualized data iterator | Emerging Cross-Sectional Technologies | 2 | Active |
| US8127082B2 | Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations | Physics | 2 | Active |
| US7716423B2 | Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes | Physics | 2 | Active |
| US7430699B2 | Trading propensity-based clustering of circuit elements in a circuit design | Physics | 1 | Active |
| US7472227B2 | Invalidating multiple address cache entries | Physics | 1 | Active |
| US7917700B2 | Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state | Physics | 1 | Active |
| US7330479B2 | Shared transmit buffer for network processor and methods for using same | Electricity | 1 | Expired |
| US7539840B2 | Handling concurrent address translation cache misses and hits under those misses while maintaining command order | Physics | 1 | Active |
| US7398505B2 | Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout | Physics | 1 | Active |
| US10996739B2 | Reducing power consumption in a neural network environment using data management | Emerging Cross-Sectional Technologies | 1 | Active |
| US9715464B2 | Direct memory access descriptor processing | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.