Pipelined packet processing
US6836808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2002 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Dec 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/357
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed on multiple processors or threads concurrently and in a pipelined fashion. Subsequent protocol packet processing tasks for processing a single packet are performed on multiple processors or threads, acting as stages of a pipeline. The assignment of tasks to processors or threads is performed dynamically, by checking the availability of a processor or thread in the subsequent pipeline stage. The availability determination includes determining the available capacity of the input work queue associated with each processor or thread. If the subsequent pipeline stage is overloaded, the task is assigned to another processor or thread that is not overloaded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.