Bilayer ultra-thin gate dielectric and process for semiconductor metal contamination reduction
US6838396B2 · kind B2 · utility
5Cited by
6References
12Claims
0Family size
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Key dates
| Filing date | Mar 28, 2003 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | May 11, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.