Leadframe for integrated circuit chips having low resistance connections
US6838755B2 · kind B2 · utility
2Cited by
10References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2001 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Jun 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A leadframe for semiconductor devices, including a region which is adapted to support a semiconductor device and a plurality of leads which are arranged so as to be directed toward the region, for mutual connection, by connecting wires connecting the leads and the semiconductor device. The leads include leads having at least two different lengths for the connection of connecting wires having different diameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.