Dual damascene bond pad structure for lowering stress and allowing circuitry under pads
US6838769B1 · kind B1 · utility
30Cited by
14References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1999 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Dec 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bond pad is located over active circuitry formed within an integrated circuit device. A barrier film forms the bottom surface of the upper portion of a bond pad opening which also includes vias extending through the bottom surface to form a dual damascene structure. The bond pad is resistant to stress effects such as cracking, which can be produced when bonding an external wire to the bond pad, and therefore prevents leakage currents between the bond pads and the underlying circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.