Memory system having control circuit configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells
US6839275B2 · kind B2 · utility
18Cited by
9References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2003 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Jul 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide a memory system. In one embodiment, the memory system comprises an array of memory cells, a write circuit configured to write memory cells in the array of memory cells and a control circuit. The control circuit is configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells, and control the write circuit to write the encoded received data into the array of memory cells at a fault address of the fault pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.