Semiconductor device with programmable impedance control circuit
US6839286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2003 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Feb 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An output impedance control circuit of a semiconductor device. A first transistor is connected to a pad and a level controller controls a gate voltage of the first transistor in response to a voltage of the pad and a reference voltage. A MOS array is connected between the pad and a power supply voltage and supplies current to the pad in response to an impedance control code. A first control circuit generates the impedance control code in response to whether a voltage of the pad is converging to the reference voltage. A second control circuit controls a pull-up impedance of the output buffer circuit in response to the first impedance control code when a voltage of the pad is converging to the reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.