Latch scheme with invalid command detector
US6839288B1 · kind B1 · utility
27Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2003 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Nov 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and circuits for reducing unnecessary changes to outputs of latch circuits are provided. Unnecessary changes to outputs of latch circuits may be reduced by preventing the outputs of the latch circuits from changing when an invalid command is detected. For some embodiments, an invalid command detector is provided that generates an invalid command signal used to inhibit latch circuits, in response to detecting an invalid command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.