Shared cache line update mechanism
US6839816B2 · kind B2 · utility
13Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2002 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Nov 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are provided in which cache updating is described for a computer system having at least a first processor and a second processor having a first cache and a second cache, respectively. When the second processor obtains from the first processor a lock to a shared memory region, the first cache pushes to the second cache cache lines for the addresses in the shared memory region accessed by the first processor while the first processor had the lock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.