Method and system for selecting data sampling phase for self timed interface logic
US6839861B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2001 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Jul 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.