Antifuse structure and a method of forming an antifuse structure
US6841846B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2003 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Jul 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention comprises an antifuse having a hemispherical grained (HSG) layer and a method of forming antifuse having a hemispherical grained (HSG) layer. The antifuse of the present invention comprises a plurality of layers, the first being a lower electrode that is disposed on an impurity region in a semiconductor substrate. A dielectric layer is disposed on the lower electrode, wherein the dielectric layer has a planar surface. A non-conductive hemispherical grain (HSG) layer is formed on the planar surface of the dielectric layer and an upper electrode is disposed on said non-conductive hemispherical grain (HSG) layer forming the antifuse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.