Premolded cavity IC package
US6841859B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2004 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Mar 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a cavity-type integrated circuit package. The process includes: supporting an interior portion of each of a plurality of leads, in a mold; supporting a die attach pad in said mold; molding a package body in said mold such that said leads extend from an interior cavity of said package body to an exterior thereof; mounting a semiconductor die to said die attach pad; wire bonding various ones of said leads to said semiconductor die; adding a fill material for covering at least a surface of said interior portion of said leads; and mounting a lid on said package body for enclosing said die in said cavity of said package body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.