Semiconductor device and method of fabricating semiconductor device with high CMP uniformity and resistance to loss that occurs in dicing
US6841880B2 · kind B2 · utility
197Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2003 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Nov 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the semiconductor device of the present invention, a plurality of dummy patterns are formed in a grid arrangement in the scribe line areas of a wafer, and a plurality of dummy patterns are formed in a diagonally forward skipped arrangement in the chip interior areas of the wafer. Altering the arrangement of dummy patterns in the chip interior areas and scribe line areas in this way enables formation of dummy patterns with greater uniformity in the chip interior areas and enables formation of dummy patterns with greater resistance to loss that occurs when dicing in scribe line areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.