Power management method and structure
US6842068B2 · kind B2 · utility
19Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2003 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Apr 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An multi-stage error amplifier (22) of a power management system (10) is formed to insert a zero to compensate for a high frequency pole that could cause unstable outputs at some output current levels. The error amplifier (22) includes a feed-forward block (40) that isolates the capacitor (36) from other signal paths to facilitate low noise and high efficiency operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.