Single instruction for multiple loops
US6842895B2 · kind B2 · utility
3Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2000 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Aug 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention relate generally to the manner in which processors execute multiple loop instructions. That is, embodiments of the invention relate to the organization of multiple loop constructs, such as, for example, nested loops, to achieve improved performance during loop execution. One embodiment contemplates a single instruction that provides for execution of other instructions of a set of instructions in accordance with multiple looping constructs. Another embodiment contemplates a single-loop instruction suitable for terminating on multiple termination conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.