Multi-chip semiconductor package structure
US6844616B2 · kind B2 · utility
5Cited by
5References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2002 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Mar 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip semiconductor package structure. The structure includes two chips and two lead frames. The leads on one of the lead frames have inner leads at one end and joint sections at the other end. The joint sections are connected with another lead frame. Both lead frames use a common set of external leads. The two chips and two lead frames are joined together forming a lead-on-chip structure with the two chips facing each other back-to-back. The assembly except the external leads is enclosed by packaging material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.