Hierarchical clock gating circuit and method
US6844767B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 18, 2003 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Jun 18, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power saving hierarchical clock gating circuit includes a first level clock gate, a plurality of second level clock gates connected to the first level clock gate, and a plurality of third level clock gates for selectively providing a clock signal to a functional block. Each third level clock gate is connected between a second level clock gate and a register, or other low level device, of the functional block for selectively providing the clock signal to the register. Accordingly, the clock signal is conveyed from the first level clock gate through a second level and a third level clock gate to a register when the corresponding first, second, and third level clock gates are activated by associated decision logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.