Non-volatile semiconductor memory device with accelerated column scanning scheme
US6845041B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 16, 2002 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Aug 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device of the present invention employs an acceleration technique for shortening a column scanning time. The acceleration technique can be realized by adjusting the width of an internal data bus, the adjusted width being selectively used according to an operation mode. When a normal read operation is executed, for example, a NAND-type flash memory device has an internal data bus width corresponding to the data input/output width. When an erase/program verify operation is executed, a NAND-type flash memory device has a wider internal data bus width than the data input/output width. According to the acceleration technique, it is possible to prevent any increase in the column scanning time in proportion to an increase in page size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.