Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems
US6845042B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2003 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Feb 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.