Method of verifying a semiconductor integrated circuit apparatus, which can sufficiently evaluate a reliability of a non-destructive fuse module after it is assembled
US6845043B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2002 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Jul 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of verifying a semiconductor integrated circuit apparatus includes (a) providing a semiconductor integrated circuit apparatus including: a first transistor which has a floating gate in which a potential is floated and to which data is written; a second transistor which has a floating gate connected together with the floating gate and reads out the data written to the first transistor; and a control gate unit, which is coupled to the floating gate, controlling an operation of reading out the data of the second transistor; (b) comparing a first data outputted through the second transistor when a first potential is applied to the control gate unit with a second data outputted through the second transistor when a second potential is applied to the control gate unit to generate a comparison result; and (c) verifying the data written to the floating gate based on the comparison result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.