Methods and apparatus for power control in a scalable array of processor elements
US6845445B2 · kind B2 · utility
9Cited by
4References
6Claims
0Family size
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Key dates
| Filing date | May 11, 2001 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Mar 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.