Inventor · Apex, NC, US

Patrick R. Marchand

60Patents
12h-index
39Co-inventors
84Inventor score

Filing activity: Sep 24, 1985 → May 8, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US6216223A Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor Physics 92 Expired
US8868838B1 Multi-class data cache policies Physics 62 Active
US8244984B1 System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy Physics 43 Active
US7263624B2 Methods and apparatus for power control in a scalable array of processor elements Emerging Cross-Sectional Technologies 42 Expired
US6446190B1 Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor Physics 40 Expired
US7836317B2 Methods and apparatus for power control in a scalable array of processor elements Emerging Cross-Sectional Technologies 38 Active
US6775766B2 Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor Physics 21 Expired
US8271734B1 Method and system for converting data formats using a shared cache coupled between clients and an external memory Physics 19 Active
US8108610B1 Cache-based control of atomic operations in conjunction with an external ALU block Physics 17 Active
US8135926B1 Cache-based control of atomic operations in conjunction with an external ALU block Physics 17 Active
US6842811B2 Methods and apparatus for scalable array processor interrupt detection and response Emerging Cross-Sectional Technologies 13 Expired
US6735690B1 Specifying different type generalized event and action pair in a processor Physics 12 Expired
US7809932B1 Methods and apparatus for adapting pipeline stage latency based on instruction type Physics 12 Expired
US8234478B1 Using a data cache array as a DRAM load/store buffer Physics 12 Active
USD534481S1 Tire tread General 11 Expired
US8595437B1 Compression status bit cache with deterministic isochronous latency Physics 11 Active
US8131931B1 Configurable cache occupancy policy Physics 11 Active
US6845445B2 Methods and apparatus for power control in a scalable array of processor elements Physics 9 Expired
US7340591B1 Providing parallel operand functions using register file and extra path storage Physics 8 Expired
US8504773B1 Storing dynamically sized buffers within a cache Physics 8 Active
US8060700B1 System, method and frame buffer logic for evicting dirty data from a cache using counters and data types Physics 7 Active
US6748517B1 Constructing database representing manifold array architecture instruction set for use in support tool code creation Emerging Cross-Sectional Technologies 4 Expired
US7422675B2 Process for changing anodes in an electrolytic aluminum production cell including adjustment of the position of the anode and device for implementing the process Emerging Cross-Sectional Technologies 4 Active
US8489858B2 Methods and apparatus for scalable array processor interrupt detection and response Emerging Cross-Sectional Technologies 4 Active
US8862823B1 Compression status caching Physics 4 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.