Semiconductor device having a wire bond pad and method therefor
US6846717B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2003 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Jun 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (50) has a wire bond pad (53). The wire bond pad (53) is formed on a passivation layer (18) over active circuitry (26) and/or electrical interconnect layers (24) of the integrated circuit (50). The wire bond pad (53) is connected to a plurality of final metal layer portions (51, 52). The plurality of final metal layer portions (51, 52) are formed in a final interconnect layer of the interconnect layers (24). In one embodiment, the bond pad (53) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad (53) allows routing of conductors in a final metal layer (21) directly underlying the bond pad (53), thus allowing the surface area of the semiconductor die to be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.