Wafer-level package for micro-electro-mechanical systems
US6846725B2 · kind B2 · utility
142Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2003 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Mar 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; filling the through-wafer via with a conductive material; and forming a cavity in the one of the two wafers having the through-wafer via wherein the cavity is superposable over a device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.