Method for etching vias
US6846747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2003 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Jun 28, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/935
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method for etching a substrate that reduces the formation of pillars is provided by the present invention. In accordance with the method, the residence time of an etch gas utilized in the process is decreased and the power of an inductively coupled plasma source used to dissociate the etch gas is increased. A low bias RF voltage is provided during the etching process. The RF bias voltage is ramped between different bias levels utilized during the etch process. An inductively coupled plasma confinement ring is utilized to force the reactive species generated in the inductively coupled plasma source over the surface of the substrate. These steps reduce or eliminate the formation of pillars during the etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.