Method and apparatus for reducing jitter and power dissipation in a delay line
US6847246B1 · kind B1 · utility
10Cited by
9References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Oct 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for reducing power dissipation and jitter in a delay line is described. The delay line includes a plurality of delay elements. At least one of the plurality of delay elements includes a gate terminal configured to receive gate control signals for activating or deactivating one or more of the delay elements. The delay line further includes gate control circuitry for providing gate control signals to the gate terminal of at least one of the plurality of delay elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.