Semiconductor memory device having structure for preventing level of boosting voltage applied to a node from dropping and method of forming the same
US6847536B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2004 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Jul 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a column decoder, a row decoder, a memory cell array block, and a sense amplifier block. The sense amplifier block is disposed adjacent to the memory cell array block. The column decoder is disposed at one side of the memory cell array block, and the row decoder is disposed at another side of the memory cell array block. First output lines of the row decoder pass over the sense amplifier block and are formed of first metal layers. Second output lines of the row decoder pass over the memory cell array block and are formed of second metal layers. Output lines of the column decoder pass over the sense amplifier block and the memory cell array block. Portions of the output lines of the column decoder passing over the sense amplifier block are formed of the second metal layers and portions of the output lines of the column decoder that pass over the memory cell array block are formed of the first metal layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.