Low skew clock input buffer and method
US6847582B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2003 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Mar 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input buffer includes first and second cross-coupled differential amplifiers. Each amplifier drives a buffer signal from a first logic state to a second logic state at a first slew rate when input signal transitions from a first logic state to a second logic state and a complementary input signal transitions from the second logic state to the first logic state, and drives the buffer signal from the second logic state to the first logic state at a second slew rate when the signal transitions are the complement of these previous transitions. An output circuit generates a first edge of an output signal when the buffer signal from the first amplifier transitions from the first logic state to the second logic state and generates a second edged of the output signal when the buffer signal from the second amplifier transitions from the first to the second logic state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.