Method for fault analysis in wafer production
US6847855B2 · kind B2 · utility
1Cited by
5References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 3, 2003 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Feb 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31718
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
With the aid of the method for fault analysis according to the invention, a wide variety of chips are mapped by means of a transformation onto at least one uniform comparable wafer map. This transformation or resealing enables a chip-area-independent assessment of the products or the fabrication processes. The method for fault analysis according to the invention furthermore has the advantage that the information thus obtained can be stored very compactly in corresponding wafer databases and is thus available for further evaluations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.