Method and apparatus for filling lines in a cache
US6848030B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2001 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Jul 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system has a processor, a cache, and a fetch unit. If there is a miss in the cache, the fetch unit generates a fetch address for the miss in the cache for the purpose of retrieving the requested data from external memory and providing the data to the processor and loading the data in a location in a line in the cache. The fetch unit also generates additional prefetch addresses for addresses consecutive with the fetch address. The prefetch addresses continue to be generated for all of the locations in the line in the cache that are consecutive with the fetch address. The generation of prefetch addresses will be stopped if another requests arrives that is not part of the already generated prefetched addresses. Further, the outstanding prefetches will be terminated if the external memory can handle such termination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.