Semiconductor device with multi-bank DRAM and cache memory
US6848035B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2002 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Jan 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is designed to hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM with a plurality of banks. The semiconductor device includes a plurality of memory banks BANK0 to BANK127, each having a plurality of memory cells, as well as a cache memory CACHEMEM used to retain information read from the plurality of memory banks. The cache memory CACHEMEM includes a plurality of entries, each having a data memory DATAMEM and a tag memory TAGMEM. The data memory DATAMEM has a plurality of sub lines DATA0 to DATA3 and the tag memory TAGMEM has a plurality of valid bits V0 to V3 and a plurality of dirty bits D0 to D3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.