Column address path circuit and method for memory devices having a burst access mode
US6848040B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 15, 2003 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Apr 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address. The adder logic circuit processes the column address bits at the same time the address bits are being coupled through the second multiplexer to the first multiplexer as a function of the correct relationship between the internal address bits and the external address bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.