Error correcting code scheme
US6848070B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 24, 1999 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Nov 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error correction code apparatus has a processor located (on-chip) L2 tag and error correction and detection, and an off-chip L2 data array and second error correction and detection, the chips connected by a data bus. For a write operation, ECC bits are generated and transmitted with data to the off-chip array. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed. For a read operation, stored ECC bits and data are retrieved from the off-chip data array and transmitted to the core processor. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.