Process for flash memory cell
US6849499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Dec 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method is provided for forming a flash memory cell having an amorphous silicon floating gate capped by a CVD oxide, and a control gate formed over an intergate oxide layer formed over the oxide cap. Amorphous silicon is first formed over a gate oxide layer over a substrate, followed by the forming of a silicon nitride layer over the amorphous silicon layer. Silicon nitride is patterned to have a tapered opening so that the process window for aligning the floating gate with the active region of the cell is achieved with a relatively wide margin. Next, an oxide cap is formed over the floating gate. Using an oxide deposition method in place of the conventional polyoxidation method provides a less bulbous oxide formation over the floating gate, thus, yielding improved erase speed for the cell. The invention is also directed to a flash memory cell fabricated by the disclosed method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.