Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratios
US6849546B1 · kind B1 · utility
20Cited by
7References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2003 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Nov 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A novel sequence of process steps is provided for forming void-free interlevel dielectric layers between closely spaced gate electrodes. Closely spaced gate electrodes having sidewall spacers are formed on a substrate. After using the sidewall spacers to form self-aligned source/drain contacts and self-aligned silicide contacts, the sidewall spacers are removed. By removing the sidewall spacers, the aspect ratio of the gap between adjacent closely spaced gate electrodes is substantially reduced (from greater than 5 to less than 2), thereby preventing voids during the subsequent deposition of an ILD layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.