Semiconductor chip, chip stack package and manufacturing method
US6849802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2003 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Feb 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip has connection lines that are routed to the side surface from bump pads on the back surface of the chip. Such semiconductor chips are stacked on a circuit board to form a chip stack package while bumps are interposed between the bump pads of the lower chip and bonding pads of the upper chip. Further, an interconnecting member such as a conductive adhesive or a wiring board is applied to the side surfaces of the stacked chips such that the connection lines are connected to the interconnecting member. Therefore, the centrally disposed bonding pads of the chips are electrically connected to the circuit board through the bumps, the bump pad, the connection lines and the interconnecting member. The semiconductor chip may have heat dissipation part formed on the back surface. Methods of manufacturing the semiconductor chip and the chip stack package are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.