Memory device having automatic protocol detection
US6851014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2002 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Jul 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array, a first protocol circuit, a second protocol circuit, an operation interface, and a protocol detection circuit. The first protocol circuit, which implements a first communication protocol, and the second protocol circuit, which implements a second communication protocol, are coupled in parallel between the memory array and the operation interface. The protocol detection circuit, which is coupled to the operation interface and to the first and second protocol circuits, monitors control signals provided to the operation interface by a host controller to determine which communication protocol the host controller employs. In response thereto, the protocol detection circuit selects one of the first and second protocol circuits to handles communication between the host controller and the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.