Method and apparatus for improving segmented memory addressing
US6851040B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2001 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Aug 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30101
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for breaking complex X86 segment operations and segmented memory addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations. A method includes providing a first segment selector for deriving a linear address of a segment descriptor in a first descriptor table and providing a second segment selector for deriving a linear address of a segment descriptor in a second descriptor table. The method also includes attempting an access of the first descriptor table to derive a segment descriptor, and if the access of the first descriptor table fails, attempting an access of the second descriptor table to derive a segment descriptor. The method also includes storing a derived segment descriptor from a successful attempted access in a descriptor register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.