H. Peter Anvin
57Patents
18h-index
51Co-inventors
87Inventor score
Filing activity: Oct 13, 1999 → Feb 1, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7100061B2 | Adaptive power control | Emerging Cross-Sectional Technologies | 80 | Expired |
| US6594821B1 | Translation consistency checking for modified target instructions by comparing to original copy | Physics | 80 | Expired |
| US7149872B2 | System and method for identifying TLB entries associated with a physical address of a specified range | Physics | 69 | Expired |
| US6968469B1 | System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored | Emerging Cross-Sectional Technologies | 62 | Expired |
| US7380096B1 | System and method for identifying TLB entries associated with a physical address of a specified range | Physics | 61 | Active |
| US8566627B2 | Adaptive power control | Emerging Cross-Sectional Technologies | 60 | Active |
| US7913058B2 | System and method for identifying TLB entries associated with a physical address of a specified range | Physics | 57 | Active |
| US8239656B2 | System and method for identifying TLB entries associated with a physical address of a specified range | Physics | 56 | Active |
| US6363336B1 | Fine grain translation discrimination | Physics | 50 | Expired |
| US7694151B1 | Architecture, system, and method for operating on encrypted and/or hidden information | Physics | 37 | Active |
| US7681046B1 | System with secure cryptographic capabilities using a hardware specific digital secret | Physics | 35 | Active |
| US6880152B1 | Method of determining a mode of code generation | Physics | 30 | Expired |
| US7111146B1 | Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine | Physics | 27 | Expired |
| US7596708B1 | Adaptive power control | Emerging Cross-Sectional Technologies | 24 | Expired |
| US7096460B1 | Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation | Physics | 24 | Expired |
| US7640450B1 | Method and apparatus for handling nested faults | Physics | 23 | Expired |
| US9411601B2 | Flexible bootstrap code architecture | Physics | 22 | Active |
| US8335930B2 | Architecture, system, and method for operating on encrypted and/or hidden information | Physics | 22 | Active |
| US7404181B1 | Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold | Physics | 18 | Active |
| US7380098B1 | Method and system for caching attribute data for matching attributes with physical addresses | Physics | 13 | Active |
| US7249246B1 | Methods and systems for maintaining information for locating non-native processor instructions when executing native processor instructions | Physics | 12 | Expired |
| US7330959B1 | Use of MTRR and page attribute table to support multiple byte order formats in a computer system | Physics | 12 | Expired |
| US7730330B1 | System and method for saving and restoring a processor state without executing any instructions from a first instruction set | Emerging Cross-Sectional Technologies | 12 | Expired |
| US7089397B1 | Method and system for caching attribute data for matching attributes with physical addresses | Physics | 11 | Expired |
| US9116729B2 | Handling of binary translated self modifying code and cross modifying code | Physics | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.