Method of manufacturing stacked semiconductor device
US6852571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2003 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Sep 5, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Flux is supplied to the surface of each land by a flux supplying apparatus. A solder ball having a predetermined size is supplied onto a land by using a ball supplying apparatus. A memory IC is disposed on a logic IC and each of a plurality of external leads comes into contact with a predetermined position in each of a plurality of corresponding lands. By performing predetermined heat treatment, the solder ball is melted to bond each external lead and each land with each other. After that, the melted solder is cooled down, the bonded portion is formed, and a stacked semiconductor device in which the memory IC is stacked on the logic IC is completed. In such a manner, a stacked semiconductor device in which external leads of a semiconductor device body are bonded to electrodes on a substrate securely is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.