Method for fabricating power semiconductor device having trench gate structure
US6852597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Aug 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/258
Abstract
A method for fabricating a power semiconductor device having a trench gate structure is provided. An epitaxial layer of a first conductivity type having a low concentration and a body region of a second conductivity type are sequentially formed on a semiconductor substrate of the first conductivity type having a high concentration. An oxide layer pattern is formed on the body region. A first trench is formed using the oxide layer pattern as an etching mask to perforate a predetermined portion of the body region having a first thickness. A body contact region of the second conductivity type having a high concentration is formed to surround the first trench by impurity ion implantation using the oxide layer pattern as an ion implantation mask. First spacer layers are formed to cover the sidewalls of the first trench and the sidewalls of the oxide layer pattern. A second trench is formed using the oxide layer pattern and the first spacer layers as etching masks to perforate a predetermined portion of the body region having a second thickness greater than the first thickness. A source region of the first conductivity type having a high concentration is formed to surround the second tre…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.