Electroetching process and system
US6852630B2 · kind B2 · utility
30Cited by
5References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2001 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Mar 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system for optionally depositing or etching a layer of a wafer includes mask plate opposed to the wafer with the mask plate having a plurality of openings that transport a solution to the wafer. An electrode assembly has a first electrode member and a second electrode member having channels that operatively interface a peripheral and center part of the wafer. The channels transport the solution to the mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.