Delay locked loop circuit with duty cycle correction function
US6853225B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Dec 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00039
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop (DLL) circuit having a structure in which a method of performing duty cycle correction (DCC) using two DLLs and an intermediate phase composer and a method of performing DCC by forming a closed loop using a negative feedback are combined with each other is provided. The DLL circuit includes a first DLL for receiving an external clock signal and generating a first clock signal and a second DLL for receiving an external clock signal and generating a second clock signal. The first clock signal and the second clock signal are synchronized with an external clock signal. The DLL circuit further includes an intermediate phase generation circuit for receiving the first and second clock signals and generating an intermediate phase clock signal and a DCC loop for receiving the intermediate phase clock signal and generating an output clock signal. The intermediate phase clock signal has an intermediate phase between the phases of the first and second clock signals. The output clock signal is generated through correction of the duty cycle of the intermediate phase clock signal using a value obtained by integrating the output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.