Register controlled delay locked loop having an acceleration mode
US6853226B2 · kind B2 · utility
23Cited by
14References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2003 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Jul 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/107
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A register controlled delay locked loop having an acceleration mode corresponding to an increase of the operation speed of a memory device is used to improve accuracy. The register controlled delay locked loop includes a delay line, a delay model, a delay block, a first phase comparator, and a second phase comparator, a mode decision block, a shift register control block, and a shift register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.