Timing vernier using a delay locked loop
US6853231B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Mar 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the vernier being programmable to one of a plurality of timing steps within a delay range and the delay range being determined by a control signal applied to a bias input, the method comprising the steps of selecting a first and second control vernier from the plurality of verniers; programming the first control vernier to a first delay; programming the second control vernier to a second delay; triggering the first and second control verniers together to generate respective first and second delay signals; generating a difference pulse signal having a duty cycle corresponding to a difference between the generated first delay signal and second delay signal; comparing the duty cycle of the pulse signal to a duty cycle of the reference pulse signal to generate a difference signal pulse, the difference signal being coupled to the bias input of the verniers to adjust the delay range such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal. In a preferred embodiment there is provided a circuit for implementing the method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.