Integrated circuits with parallel self-testing
US6853597B2 · kind B2 · utility
16Cited by
20References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Sep 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a BIST control unit for testing a plurality of memory banks simultaneously is described. The BIST control unit is coupled to a plurality of comparator units. In one embodiment, a comparator unit is coupled to a memory bank to facilitate parallel testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.