Non-volatile memory device with burst mode reading and corresponding reading method
US6854040B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2000 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Nov 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read control circuit and a reading method for an electronic memory device integrated on a semiconductor includes a non-volatile memory matrix with associated row and column decoders connected to respective outputs of an address counter. An address transition detect (ATD) circuit detects an input transition as the memory device is being accessed, and read amplifiers and attendant registers transfer the data read from the memory matrix to the output. The read control circuit includes a detection circuit to which is input a clock signal and a logic signal to enable reading in the burst mode. A burst read mode control logic circuit is connected downstream of the detection circuit. The method includes accessing the memory matrix in a random read mode, detecting a request for access in the burst read mode, and executing the parallel reading of a plurality of memory words during a single period of time clocked by the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.